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| For Communications Equipment MN6153UC PLL LSI with Built-In Prescaler Overview The MN6153UC is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data input. It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump. It offers high-speed operation on a low power supply voltage (1.0 to 1.4 V) and low power consumption (0.5 mW for VDD=1.03 V, F IN= 60 MHz). Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. Pin Assignment XIN XOUT FV VDD DOP VSS VCP FIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OR OV LC FR PS LE DATA CLK Features Low power supply voltage: V DD=1.0 to 1.4V Low power consumption: 0.5mW (V DD=V1.03V, F IN=60MHz) High-speed operation: F IN=60MHz (V DD=1.03V) Frequency dividing ratios in reference frequency dividing stage: 5 to 131,071 Frequency dividing ratios in comparator stage: 272 to 262,143 Lock detector output pin Two types of phase comparator output - Internal charge pump output - Output for external charge pump Output monitor pins for both comparator and reference frequency dividing stages (TOP VIEW) SSOP016-P-0225 MN6153UC Block Diagram XIN 17-bit programmable counter XOUT 17-bit latch CLK 9 2 1 13 FR Phase matching 14 LC Control DATA 10 Data control 18-bit shift register Phase comparator 15 OV 16 OR 7 5 DOP 3 VCP LE 18-bit latch 12 11 PS 8 Swallow counter For Communications Equipment FIN Prescaler and phase matching 14-bit programmable counter FV For Communications Equipment Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol XIN XOUT FV V DD D OP V SS VCP FIN CLK DATA Function Description Crystal oscillator connection pins: XIN =Oscillator circuit input pin; XOUT=Oscillator circuit output pin. Frequency divider output signal in comparator stage. Phase comparator input monitor. Power supply Low-pass filter connection pin. Use a passive filter. Ground Power supply pin for built-in charge pump Frequency divider input pin in comparator stage. Shift register clock input pin. The chip latches data at the rising edge of the CLK signal. Shift register data input pin. The final two bits in the data select the write latch: "11" for R-latch; "01" for N-latch. 11 12 LE PS Load enable signal input pin. MN6153UC This is the latch-write-enable signal. It is at "H" level for write. Power save control signal input pin. "H" level input starts the frequency divider and places the chip in operational mode. "L" level input places the chip in standby mode, which saves power. The chip switches the internal charge pump output to the H-z state and the loop is opened. 13 14 FR LC Reference frequency divider output signal. Phase comparator input monitor. Charge pump control signal output pin. When frequency divider operation is stopped, this pin is at "L" level, the internal charge pump output is in the high-impedance state, and the loop is opened. 15 16 OV OR Phase comparator output pin for external charge pump. (OR provides N-channel open drain output.) MN6153UC MN6153 Frequency Dividing Data Settings For Communications Equipment The following formula shows frequency divider operation. FIN ={ (16 x N) + A} x (XIN / R) where FIN : VCO output frequency N : Setting for 14-bit programmable counter on comparator side A : Setting for 4-bit swallow counter on comparator side XIN : Reference oscillator frequency R : Setting for 17-bit programmable counter on reference side Note that N should be greater than A. N-Side Latch Data MSB Test data 3 bits 14 bits Programmable counter setting (N) 4 bits Swallow counter setting (A) LSB For Communications Equipment Note on Setting Frequency Dividing Data Input 1) Frequency dividing data input (1) Reference side Data input direction MSB 17-bit frequency dividing data LSB 1 bit 1 bit Control bits MN6153UC "L" Frequencey Write selection dividing stage selection "H" level "H" level 1 CLK 2 17 18 19 DATA MSB LE LSB (2) Comparating side Data input direction *1 3-bit test data 3 bits "L" level 18-bit frequency dividing data 1 bit 1 bit "L" Control bits 1 CLK 2 3 4 5 Frequencey Write selection dividing stage selection "H" level "L" level 21 22 23 DATA MSB LE LSB Notes 1.*1: Preceding the input of the frequency dividing data for the comparating side, input test data consisting of three "L" level bits to produce normal operation. Never use any other pattern. 2. When the power is first applied, internal operation remains in an unstable state until data is written. To eliminate the risk of excessive current consumption, keep the PS pin at "L" level. 3. When the power is first applied, the data settings are indeterminate. Always write data to the chip before starting operation. 4. Enter the data to fill the entire latch: Reference side: 19 bits (17 bits for the frequency divider setting and 2 control bits) Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2 control bits) 5. Drive the LE pin at "L" level while writing the data. 6. "H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin are both at "L" level. 7. Writes are possible when the PS pin is either "H" or "L" level. 8. Input the data MSB first. 9. The data are inputted at the rising edge of the CLK signal. MN6153UC Absolute Maximum Ratings Parameter Power supply voltage Power supply voltage Input pin voltage Output pin voltage Power dissipation Operating ambient temperature Storage temperature Symbol VDD VCP VI VO PD Topr Tstg For Communications Equipment Rating - 0.3 to +3.0 - 0.3 to +4.0 VSS - 0.3 to VDD +0.3 VSS - 0.3 to VDD +0.3 20 -10 to +60 -55 to +125 Unit V mW C Operating Conditions VSS=0V, Ta=-10 to +60C Parameter Power supply voltage Power supply voltage Symbol VDD VCP Test Conditions min 1.0 2.5 typ 1.1 3.0 max 1.4 3.2 Unit V V Electric Characteristics VCP=2.5V, Ta=-10 to +60C Parameter Power supply pin Power supply current Symbol VDD IDD IDstop Test Conditions VDD =1.03V FIN =100MHz, XIN =20MHz, PS="H" PS="L" (at power save operation) min typ max 0.5 2.0 Unit mA A Input Pins CLK, DATA, LE, PS VIH VIL ILI VDD=1.03 to 1.4V VDD=1.0 to 1.4V "H" level input voltage "L" level input voltage Input leakage current Input Pin Input voltage Input current Input leakage current Maximum operating frequency Minimum operating frequency Input Pin Input voltage Input current Input leakage current XIN FIN VDD - 0.2 VSS VDD 0.2 1.0 V A Vp-p VIN IIF ILIF FINMAX FINMIN VIN IIX ILIX Pull-up resistor is present (PS="L") VIN=0 or V DD Pull-up resistor is present (PS="L") VIN =0 or VDD (PS="H") VIN =0.4 Vp-p VIN =0.4 Vp-p 0.4 -10 -100 20 60 10 0.4 - 0.2 -1.5 2.0 A A MHz MHz Vp-p mA A VDD=1.0 to 1.4V For Communications Equipment Electrical Characteristics (continued) VCP=2.5V, Ta=-10 to +60C MN6153UC Parameter Crystal Oscillator Pins Crystal oscillator frequency Symbol Test Conditions XIN, XOUT VDD=1.03 to 1.4V fXtal VDD=1.0 to 1.4V min typ 12.8 max Unit MHz Output Pins FV, FR, LC, OV "H"level output voltage "L"level output voltage Output Pin "H"level output voltage "L"level output voltage Output Pin DOP "H"level output voltage "L"level output voltage Output leak current Output leak current Output Pin OR "L"level output voltage Setup time *1 Hold time *1 VOH VOL VXOH VXOL VDD =1.0 to 1.4V I OH= -60A I OL=30A IXOH= -100A I XOL=100A VDop=V CP - 0.3V VDop=0.3V VDop=V CP VDop=0.0V VOR=0.3V VDD- 0.3 VSS VDD- 0.3 VSS -250 250 VDD 0.3 VDD 0.3 V XOUT VDD =1.0 to 1.4V V IDOH IDOL ILOH I LOL VDD=1.0 to 1.4V 2.0 -2.0 45 500 500 500 A IORL VDD=1.0 to 1.4V A ns ns ns tsul tsu2 tH Note*1: The following timing chart shows the setup and hold times. DATA 50% tsu1 tH CLK tsu2 LE Usage Note Be particularly careful with this product as it is more sensitive on the static electricity damage than most of our other products. MN6153UC 10pF MN6153UC 1 XIN OR OV LC FR 12 PS LE DATA VCP 8 FIN CLK 11 10 9 Intermittent operation control Frequency dividing data generation input Frequency dividing data generation input Frequency dividing data generation input 14 13 15 16 2 12.8MHz 3 XOUT FV 4 VDD DOP VSS 12pF 12pF Application Circuit Example VDD=1.0V to 1.4V 10k 0.1F 5 6 0.1F 1F *1 Loop filter VCP=3V 1000pF 7 100 0.22F 35k VF VCO 50 to 60MHz Amplifier 390 VCC 10F VCC=3V For Communications Equipment Note *1: VCO characteristics may necessitate design revisions. For Communications Equipment Package Dimensions (Unit: mm) SSOP016-P-0225 MN6153UC 6.50.2 16 9 1.00.1 4.30.2 6.30.2 0.15 -0.05 +0.10 0 to 10 0.50.1 (0.45) 1.450.20 0.10.1 SEATING PLANE 1.550.30 1 8 0.8 0.15 0.350.10 |
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